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Serial Quad I/O (SQI) Flash Memory
A Microchip Technology Company
SST26VF016 / SST26VF032
Data Sheet
Pin Description
CE#
SO/SIO1
1
2
8
7
VDD
SIO3
CE#
SO/SIO1
1
2
8
7
VDD
SIO3
Top View
Top View
SIO2
VSS
3
4
6
5
SCK
SI/SIO0
SIO2
VSS
3
4
6
5
SCK
SI/SIO0
8-Lead SOIC
1359 08-soic S2A P1.0
1359 08-wson QA P1.0
8-Contact WSON
Figure 2: Pin Description for 8-lead SOIC and 8-contact WSON
Table 1: Pin Description
Symbol
SCK
SIO[3:0]
SI
Pin Name
Serial Clock
Serial Data
Input/Output
Serial Data Input
for SPI mode
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the
clock input, while output data is shifted out on the falling edge of the clock
input.
To transfer commands, addresses, or data serially into the device or data out
of the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The EQIO command
instruction configures these pins for Quad I/O mode.
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a
power on reset.
SO
Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling
for SPI mode
edge of the serial clock. SO is the default state after a power on reset.
CE#
V DD
V SS
Chip Enable
Power Supply
Ground
The device is enabled by a high to low transition on CE#. CE# must remain
low for the duration of any command sequence; or in the case of Write oper-
ations, for the command/data input sequence.
To provide power supply voltage: 2.7-3.6V
T1.0 25017
?2011 Silicon Storage Technology, Inc.
4
DS-25017A
04/11
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